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analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com introduction this is a reference note for protek analog?s PA1418. the document includes data for the ic, recommended external components, and other pertinent information. please read all instructions and recommendations before be ginning to design any product that is to include this device. this document contains a checklist to reference before powering up completed circuit and troubleshooting procedures outlining causes and countermeasu res for issues arising in the application of the ic. contact information is included if this document is in sufficient to answer any problems or questions that may arise. contents 1. overview. 1.1. features 1.2. block diagrams 24tssop pin out 32 qfn pin out 1.3. absolute maximum ratings 1.4. operating range 2. operation. 3. navigator. 4. explanation of external parts. 4.1. pre-emphasis 4.2. limiter 4.3. low-pass filter 4.4. half v dd filter 4.5. composite signal adjust 4.6. rf oscillator 4.7. rf output 4.8. x?tal oscillator 4.9. serial data input 4.10. phase lock loop 4.11. audio mute 4.12. pilot signal adjust 5. pcb sample and recommendations. 1. overview: the PA1418 is a radio transmitter that can send audio signals from personal computers, game consoles or independent devices to any type of audio equipment with a built in fm receiver. the ic consists of a pre-emphasis circuit that improves signal to noise ratio (s/n), a limiter circuit that prevents over-modulation and a low pass filter (lpf) circuit that limits the maximum modulation frequency. the stereo modulation circuit generates stereo composite si gnals through a fm transmitter circuit with phase- locked loop (pll) frequency synthesizers. 1. 1. features 1. improved audio quality due to integrated pre-em phasis, limiter and low-pass filter circuits. 2. pilot tone fm stereo modulation circuit is integrated. 3. an incorporated pll frequency synthesizer ensures a stable fm transmission frequency. 4. device utilizes a serial data control method to set the frequency via a microcontroller. 5. integrated mute option. free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 1. 2. block diagram: 24 tssop package l-ch input r-ch input pre-emp tc pre-emp tc lpf tc filter composite signal out gnd pll phase detector out v cc rf oscillator nc rf ground rf output lpf tc pilot sig adj audio mute data clock chip enable xtal in xtal out nc pll vcc 24 23 22 21 20 19 18 13 14 15 16 17 1 2 3 4 5 6 7 12 11 10 9 8 - - + + lpf lpf v cc 2 + audio mpx mute 16 bit shift register pilot mpx 1/2 m/s 1 osc rf dual modulus driver 1/25 1/76 phase detector 2 11 304khz 100khz 152khz free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 1.2. block diagram: 32 qfn package pilot sig adj. audio mute ce l-ch input pre-emp tc lpf tc r-ch input pre-emp tc lpf tc filter nc nc 27 31 28 26 32 25 29 30 1 13 4 5 6 7 8 14 10 15 9 16 12 11 xtal in xtal out pll v cc rf oscillator rf ground rf output nc nc 3 2 24 23 22 21 20 19 18 17 data clock nc nc composite signal out pll phase detector out v cc nc nc nc nc gnd 16 bit shift register phase detector - - + + lpf lpf v cc 2 audio mpx + mute pilot mpx 1/2 m/s 1 2 dual modulus driver osc rf 1/25 1/76 11 304khz 152khz 100khz free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 1. 3. maximum operating range (ta = 25 o c, in test circuit)(pin numbers reference the 24 tsop package) parameter symbol limits unit conditions supply voltage v cc +7.0 v pin 8, 13. data input voltage v in-d - 0.3 to vcc + 0.3 v pin 17,18,19,20. phase comparator output voltage v out-p - 0.3 to vcc + 0.3 v pin 7. power dissipation p d 630 mw ( note 1) storage temperature t stg -55 to +125 oc (note 1) when operation temperature exceeds ta= to 25oc power is derated at 6.3mw per 1oc 1.4. recommended operating range (ta = 25 o c,) parameter symbol limits unit conditions operating supply voltage v cc 3.6 to 5.0 v pin 8, 13. operating temperature t opr -40 to +85 oc audio input level v in -a up to 10 dbv pin 1, 24 audio input frequency band f in -a 20 to 15k hz pin 1, 24 pre-emphasis time constant set up range t pre to 155 s pin 2, 23 transmission frequency f tx 70 to 120 mhz pin 10, 12 control terminal ?h? level input voltage v ih 0.8vcc to vcc v pin 17, 18, 19, 20. control terminal ?h? level input voltage v il gnd to 0.2vcc v pin 17, 18, 19, 20. notes i. operating conditions . a. do not exceed the maximum rating for this device even mo mentarily; reliability and func tionality of the device could be compromised. if special design considerations permit t he circuit to exceed the listed tolerance, please utilize a fuse or other methods to protect component from damage. b. the electrical characteristics described at ta = 25c cannot be guaranteed if this operating temperature is not maintained. please contact the engineers at protek analog if you have any questions or concerns. ii. storage and transportation. a. store the product in a dry place at room temperature to prevent oxidation of the device terminals. (humidity = 75% or less, temperature = 0-30c) b. please use static protec tion containers when storing or transporting devices. c. be careful not to expose ics to water or electrically conducting fluids at any time and avoid toxic gasses or dust. d. during transportation, please insulate the device from any discharge capacitors on boards. e. avoid mechanical vibration and physical sho ck to devices during transportation or storage. free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com iii. cautions duri ng installation. a. some device packages contain nc terminals, please do not use these free pads for relays, or allow the other pins to make contact with t hese nc terminals. problems such as unwanted oscillations may occur. b. caution: if a heat sink is cut or damaged and the device is deformed the induc ed thermal stress can cause a failure or limit the lif e of the device. c. when mounting device on a board please be careful to al ign the device in the correct direction, both the 32 qfn and 24 tssop packages have dots placed in the same corner of the package corresponding to pin 1. powering on the device with the pins misaligned can ruin the device. d. install the device gently on its pcb level with the plane of the board to reduce stress on pins and contacts. e. before soldering device, be sure that the soldering iron properly grounded and t hat it is not leaking power into the tip. discharge from the iron can cause failure of the device when placed in contact with the pins. f. verify that all assembly stations and their perspective assembly techs are properly grounded as released static charge can have an adverse effect on the device. likewise , pay close attention to the humidity and production methods to reduce static buildup. iv. cautions during testing and inspection. a. be sure to inspect soldering for accuracy before ap plying power to the device, bridged pins can cause serious damage. b. please use a current limiter circuit on the power su pply, high currents can go into the device and ruin it. c. be careful that the device or board is in the designated position before starting measurement inspection or possible high currents can damage product. d. ensure that the ground will not generate a surge current. v. heat design a. the operational characteristics of this device are affected by temperat ure. excessive heat can cause the performance and life expectancy of the product to reduce dramatically, in extreme cases destroying the device outright. b. the ic is designed for balanced temperature at normal op eration; if however, exte rnal components or lack of proper ventilation cause excessive heat than additi onal heat sinks can be utilized to cool the device. c. if additional heat sinks are implemented, please ensure that they are properly bonded to device. if you have any questions about ther mal design or any other topics in an applicati on please contact the applications team at protek analog. 12 13 PA1418 xxxx 1 24 PA1418 32 qfn 24 tssop free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 2. operation: (pin numbers reference 24 tssop package) the PA1418, fm stereo transmitter ic made by protek analog includes all the processing circuitry required for stereo fm transmission and also the crystal control section, which provides precise frequency locking as shown, the PA1418 includes two separate audio processing sections, for the left and right channels. the left-channel audio signal is applied to pin 24 of the chip, while the right channel signal is applied to pin 1. these audio signals are then applied to a pre-emphasis circuit, which boosts those frequencies above a 50ms time constant (i.e., those freque ncies above 3.183 khz) prior to transmission pre-emphasis is used to impr ove the signal-to-noise ratio of the received fm signal. it works by using a complementary de-emphasis circuit in the receiver to attenuate the boosted treble frequencies after demodulation, restoring t he frequency response is restored to normal. at t he same time, this also significantly reduces the ?hiss? sound that would otherwise be evident in the signal the amount of pre-emphasis is set by the value of the capacitors connected to pins 2 & 23, (signal limiting is also provided within the pre-emphasis section). this involves attenuating signals above a certain threshold to prevent overloading succeeding stages also preventing over-modulation and reduces distortion. the pre-emphasized signals for the left and right channels are then processed through two low-pass filter (lpf) stages, designed at15khz. this roll-off is necessary to restrict the bandwidth of t he fm signal and is the same frequency limit used by commercial broadcast fm transmitters. the outputs from the left and right lpf channels are in turn applied to a multiplex (mpx) block. this is used to effectively produce sum (left + right) and difference (left - right) signals which are then modulated onto a 38 khz carrier. the carrier is then suppressed (or removed) to provide a double-sideband suppressed carrier (dsbsc) signal. it is then mixed in a summing (+) block with a 19 khz pilot tone to give a composite signal output (with full stereo encoding) at pin 5. the phase and level of the 19 khz pilot tone are set using a resistor and a capacitor at pin 21.the 38 khz multiplex signal and 19 khz pilot tone are derived by dividing down the 7.6mhz crystal oscillator located at pins 14 & 15. the 7.6mhz crystal frequency is divided by 25 to provide a 304 khz signal. this 304 khz signal is used by the audio multiplexer and an 8-bit dac to generate the composite signal with the subcarriers (38 khz). the 76mhz frequency is also divided by 50 to generate a 152 khz frequency. this signal is used by the pilot signal into the composite audio. in addition, the 1.9mhz signal is divided by 76 to give a 100 khz signal. this signal is then applied to the phase detector, which also monitors the program counter output. this program counter is actually a programmable dual modulus divider, which outputs a divided down value of the rf signal. the division ratio is set by programming the counter with a 6 and 5 bit number. more information on the working of the dual modulus divider is given in section i of ?explanation of external parts? the phase detector output produces an error signal to control the voltage applied to a varicap diode and forms part of the rf oscillator at pin 10. its frequency of oscillation is determined by the value of the inductance and the total parallel capacitance. since the varicap diode forms part of this capacitance, we can alter the rf oscillator frequency by varying its value. in operation, the varicap diode's capacitance varies in proportion to the dc voltage applied to it by the output of the pll ph ase detector. the phase detector adjusts the varicap vo ltage so that the divided rf oscillator frequency is 100 khz at the program counter output. if the rf frequency drifts high, the frequency output from the programmable divider rises and the phase detector will "see" an error between this and the 100 khz signal. as a result, the phase detector reduces the dc voltage applied to the varicap diode, thereby increasing its capacitance. and this in turn decreases the oscillator frequ ency to bring it back into "lock". conversely, if the rf frequency drifts low, the programmable divider output will be lower than 100 khz. this means that the phase detector now increases the app lied dc voltage to the varicap to decrease its capacitance and raise the rf frequency. as a result, this pll feedback arrangement ensures that the programmable divider output remains fixed at 100 khz and thus ensures stability of the rf oscillator. by changing the programmable divider we can change the rf frequency. so, for example, if we set the divider to 1079, the rf oscillator mu st operate at 107.9mhz for the programmable divider output to remain at 100 khz. the rf frequency is modulated by the voltage applied to the varicap diode using the composite signal output at pin 5.the average frequ ency of the rf oscillator remains fixed, as set by the programmable divider. as a result, the transmitted fm signal varies either side of the carrier frequency according to the composite signal level - i.e., it is frequency modulated. free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 3. navigator: basic design reference pin out reference 24tssop pin name 32qfn 1 r- ch input 29 2 pre-emp tc 30 3 lpf tc 31 4 ? vcc 2 5 signal out comp 3 6 gnd 5 7 pll phase detect 7 8 vcc 8 10 rf oscillator 10 11 rf ground 12 12 rf output 13 13 pll vcc 14 14 xtal out 15 15 xtal in 16 17 chip enable 18 18 clock 19 19 data 20 20 audio mute 21 21 pilot signal adjust 22 22 lpf tc 26 23 pre-emp tc 27 24 l- ch input 28 e left channel in right channel in l-ch input pre-emp tc lpf tc pilot sig adj audio mute data clock chip enable xtal in xtal out nc pll vcc r-ch input pre-emp tc lpf tc ? vcc filter signal out comp gnd pll phase detect vcc rf oscillator nc rf ground rf output 1uf 50k 50k 1uf 10uf 2.2nf 2.2nf 150pf 150pf 1.8k 2.2nf 7.6mhz 27 p f 27pf 10uf 1uf .1uf 10uf .22uh .22uh 22 p f 22pf 22pf 56k 56k 3.3k 22pf .1u 10 10uf mpx cmp vt 2pf (opt) 150pf vcd 470pf 3.3k 3.3k 10k 2.2nf 10k 330pf 10uf 50k 2.2k 10k .047uf 1uf b c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 + 10f + + + 100nf + + + + free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 4. explanation of external parts: (use tssop package for referencing pin locations) 4.1. pre-emphasis (pins 2, 23) the ic?s internal bias is set to ? vcc at pins 1 and 24 therefore coupling capacitors (c 1 ) must be used between these pins and the audio signal. the positive polarity of the coupling capa citors must be set to the higher dc potential whether that is the input signal from the audio source or the left and right channel inputs. the low range frequency cut-off is determined by the input imped ance values of pins 1 and 24 and the value of the external coupling capacitors. if the value is too low the lower frequency ranges can be cut, but if the value becomes too large a pronounced pop-up noise and a longer start up time will result. the input cut-off frequency can be calculated by: ? cl = 1432 1 ck ?? ? the pre-emphasis time constant is determined by the value of the external capacitors (c 2 ) at pins 2 and 23 and the ic?s internal resistance of 22.7k ? . the time constant can be calculated by: 2 7.22 ck ??? ? ? < sec155 ? 4.2. limiter (internal) the limiter circuit: - - + + low pass filters ? vcc 100 k 100 k 100 k 100 k pre-emphasis c 1 c 2 1 24 23 2 - - + + l & r channel inputs c 1 limiter circuit c 2 + + ? vcc 43 k 43 k 1 k 1 k 22.7 k 22.7 k free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 4.3. low pass filter (pins 3 and 22) both pin 3 and pin 22 require 150pf capacitors (c 3 ) connected to ground to complete the lpf circuit. 4.4. half vcc filter (pin 4) a 10 f capacitor (c4) is required for proper filtering. a lower value will add distortion while a higher value will slow the start up time. 4.5. composite signal adjust (pin 5) the modulation rate is adjusted using the composite signal output (pin 5) and the external fm modulator. to make an adjustment, alter the load resist ance at pin 5 by changing the value of r 1 . the total load on pin 5 should not exceed 50k ? ; lesser values will add unnecessary distortion. ? cl = 51 c2 1 r ? 4 c 4 ? vcc + 5 c 5 to the fm modulator + audio mpx mute pilot mpx r 1 + + 22 3 c 3 c 3 -- + + mpx ? vcc 100k 100k 100 k 100 k limiter circuit 50pf 50pf 100k 100 k free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com by design, the ic is set so that the composite output l + r = 85% and pilot = 15% when 400hz and -20dbv of sine wave is input to pins 1 and 24. the pilot modulation rate is set to 15% to prevent the amplitude from lowering and the modulation rate from dropping far below 10% when the phase of the pilot signal is adjusted. if it is necessary to adjust the pilot modulation precisely, insert a resistor first in between pin 19 and capacitor to lower the modulation rate. then adjust r 1 while measuring the fm modulation rate at pin 11 until it reaches 100% with a modulation analyzer. 4.6. rf oscillator (pin 10) the rf oscillator is a modified clapp oscillator, which consis ts of bipolar transistors. the features of this circuit are such that the oscillating condition is not affected even if the impedance of the parallel resonant (lc) circuit is changed. the oscillation is stabilized against internal transistor changes because the feedback capacitor inside the ic is much larger than the capac itance of the transistor. the rf oscillator is an im portant part of the pll circuit and should be verified in the application. undesir able noise may result from running oscillations at the limits of the range or from external fa ctors. the scale of the distortions are directly proportional the frequency so extra care is needed when using the upper ranges of the o scillator. it is also important to be sure the oscillator?s components are properly secured; vibrations can c ause undesired modulation if not mechanically sound. the padding capacitor c 3 in series with the variable capacitance diode vcd is used to adjust the oscillating frequency range. the choice of c 3 depends on the characteristics of the vcd. c 3 can vary from 10pf to 150pf depending on surrounding components. if c 3 is set closer to 100pf then the vcd has a large impact on the lc resonant circuit. when c 3 is set with a low capacitance, the variable range of the control voltage to the vcd becomes wider, thereby making the oscillator excessively sensitive. this can cause the modulation rate to fluctuate in an exaggerated fashion in re lation to the transmission frequency. the inductance of the coil l 1 is set so that the reactance x l may be around 50-100 if ? tx = 77.5 mhz then, l 1 = tx ?2 ? l x the capacitor c2 is connected in parallel with l1 and is used to set the range of the oscillator frequency. the larger the c min capacitor value, the smaller the variable range will become. if ? min = 76 mhz then, c totmin = 1 2 1 l ? = 42.6pf if ? max = 79 mhz then, c totmax = 1 2 1 l ? = 39.4pf 10 c 1 11 dual modulus divider osc rf r 1 12 vt r 2 vcd c 2 c 3 l 1 r 3 c 4 cmp free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com c tot is the combination of the inline capacitance of vcd and c 3 with c 2 . choose a vcd that had a linear c-v relationship of 0 v in 5.0. in this schematic the part number used was zetex zmv832act that has a capacitance range of 30pf @ v in = 0v to 11pf @ v in = 5.0v. (please refer to manufacturer?s datasheet for detailed information on this part) the type of capacitor used for c 2 is also of importance because of the need to cancel the temperature characteristics of l 1 . a temperature compensating ceramic capacitor is utilized for this purpose. for air-core coil inductors rh (-22060 ppm/co) or sh (-33060 ppm/co) can be used, for ferrite-core inductors th (-47060 ppm/co) or uj (-75060 ppm/co) are recommended. the damping resistor r 1 and the coupling capacitor c 1 are used to correct the harmonics of the oscillating circuit. c 2 should be set between 470pf and 47nf. if larger values are utilized, the internal osci llator is greatly affected by the external circuits and may not stabilize. if the val ue is set low the q of the oscillating circuit is decreased and the oscillating may stop. the harmonics are observed by monitoring the antenna terminal with a spectrum analyzer. please be sure to match the impedance (50 ? or 75 ? ) or the results will be misleading. the damping resistor is used to reduce the harmonics level. set r 1 between 0 ? and 10 ? . r 1 must be set so that the harmonics comply with the radio laws of the marketed countries. to confirm the oscillat ion range of operation, 1. manually discharge the inductor to stop the oscillati on and upon removing the source of the interruption, check to see if the oscillating resumes. 2. confirm that oscillation can continue when the power supply drops below 3.0v 3. given that step 1 and 2 pa ssed. increase the value of r 1 by at least 33% and check to see if the circuit can still oscillate. 4. if the circuit is incapable of passing t he first 3 tests, increase the value of c 1 or alter l 1 or the vcd to increase the q of the circuit. r 2 is used to increase the impedance after the vcd; to achieve this at least 10k ? should be employed. r 3 and c 4 act as a low pass filter for the dc voltage at vcd, choose r 3 as 3.3k ? and c4 as 2.2nf. 4.7. rf output (pin 12) a bpf must be inserted in-between the rf output and the antenna to suppress und esired rf output harmonics. the output impedance of pin 12 is set to 75 ? . c 1 11 dual modulus divider osc rf r 1 12 r 2 c 4 c 2 c 3 l 1 r 3 l 2 antenna bpf free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 4.8. x?tal oscillator (pin 14, 15) a 7.60 mhz crystal oscillator is needed between pins 14 and 15 coupled with its 27pf load capacitors (c 1 and c 2 ) as shown the the folowing drawing. the crystal needs to be placed as near as possible to t he device output pins to minimize stray capacitance. please no not run any wires or traces near or under the osci llator as it is very sus eptable to interference. if possible, place a ground plane directly under the crysta l to further insulate it from any nearby signals. 4.9. serial data input (pin 17, 18, 19) the v ih level for the inpt voltage at the seri al data input is 0.8vcc to vcc and the v il level is gnd to 0.2vcc. please note that the operating vo ltage of the microcontroller can be different from the operating voltage of the ic. it is also important to keep in mind that there needs to be a small delay betweeen powering on the ic and inputing the serial data. the initial logic is set as ?unfix ed? upon startup and some circuits such as the pll will not function correctly instantaniously. PA1418 ? serial programming interface: the PA1418 has a 3-pin serial programming port. this port consists of pins ce (chip enable), ck (clock) and da (data). the timing sequence of these signals is as sh own in figure 1. using these ports a 16-bit word can be fed into the chip to form va rious division ratios as well as other control bits. 15 r f 14 c 2 c 1 7.60mhz 13 18 17 6 19 shift register dual modulus divider micro-controller mono/stereo phase detector 1 2 11 free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com figure 1: timing sequence of signals setup and hold requirements: the setup and hold requirements of t hese signals are shown in figure 2: tdb tde thw tlw tr tf tse thl 1.5sec 0sec 1.5sec 1.5sec 300nsec 300nsec 100nsec 100nsec figure 2: setup and hold requirements of signal tse thl c e c k d a 90% 50% 50% 50% 50% 50% 50% 90% 10% tr tf tde tdb thw tlw ce ck da t1 t2 t3 t4 d0 d1 d2 d3 d4 d5 t0 t1 t1, t2, t3, t4 1.5 sec free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com bit structure of the 16-bit word: the bit structure of the 16-bit word is shown in figure 3. serial data input configuration figure 3: serial data input configuration setting up the program counter: figure 4 shows the contents of the program counter. program counter configuration figure 4: program counter configuration the dual modulus divider works as follows: m = 32* ps ? = in rf f f = khz f rf 100 where: m is the desired division ratio. s and p are integers such that s < p . example: to program for 101.1mhz frequency, perform the following calculations. rf f mhz 1.101 ? m = khz mhz 100 1.101 = 1011 calculate p as: p= 32 1011 = 31 = 111110 b calculate s as: s= 1011 - 32 ? 31 = 19 = 11001 b to program the chip for normal stereo operation, feed the following bits: (0000 1100 1101 1111) b t 1 t 0 pd 1 pd 0 m/s s 0 s 1 s 2 s 3 s 4 p 0 p 1 p 2 p 3 p 4 p 5 s 0 s 1 s 2 s 3 s 4 p 0 p 1 p 2 p 3 p 4 p 5 da test phase detector output control mono/ stereo program counter s (5 bits) p (6 bits) free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com figure 5: block diagram of pll. the pfd and divider are internal to the chip please note that due to the limitations of the d ual modulus divider, there are frequencies where s ? p, such as 95.9 mhz (where s = 31 and p = 28). if programmed for this frequency or any other frequency where s ? p, the pll will not lock to the desired frequency and it may produce undesired results like audio noise or jitter. the following frequencies in the us fm band may not be programmable by the PA1418: 89.1, 89.3, 89.5, 92.5, 92.7, 95. 7, 95.9, 99.1, and 102.3. explanation of the remaining controller bits: in addition to the 11 bit word for the divider, the PA1418 provides an additional 5 bits for controlling the phase detector output and the mu ltiplexer stereo/mono transmission. they are as follows: mono/stereo: mono status 0 monaural operati on, l + r, pilot off 1 stereo operation, l + r + (l-r)sin t + psin( t/2) phase detector: pd0 pd1 charge pump output 0 0 normal operation 0 1 forced low 1 0 forced high 1 1 high z dual mod divider m f f rf n i ? pfd filter vco rf frequency ( rf f ) in f (input frequency) ref f (ref frequency 100khz) rf f free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com c1 c2 r2 c3 r3 r1 v in vdd 2.2k 10k 1 0.047f 3.3k 2200pf v out 4.10. pll loop filter the PA1418 employs a charge pump pll. this means that t he pfd output (pin 7) is a current output. an active loop filter is recommended because it has a very sma ll input leakage current. the PA1418 employs a darlington pair (mpsa13) as the amplifier. the active filter is a low-pass type filter. the block diagram of the pll is as shown in figure 6. figure 6: block diagram of the charge pump pll the active filter that is used in the pll, as shown in figure 7. figure 7: active loop filter for PA1418 and its response c1 pfd c2 gm r1 fr n vco fin v c f1 f2 free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com frequencies f1 and f2 are obtained as follows: hz cr f 9.15 2 1 12 1 ? ? ? ? khz cr f 9.21 2 1 33 2 ? ? ? ? the pll directly conducts audio modulation to the vco. hence the interrupting frequency f1 should be set low. the time to lock to the set frequency is dependent on the time constant 1 which is calculated as follows: ? ? ? ? ? ? ??? gm rc 1 211 ? where 1 rgmgm ? ? this time constant has a trade-off relation with the amplitude and distortion characteristics when the modulation is conducted at a low range frequency (100 hz). in other words, if the frequency lock time is shorter, the distortion ratio in the lower range becom es worse, and if the amplit ude characteristics and the distortion ratio are improved, the frequency lock time bec omes longer. if r2 value is chosen to be smaller, the gain ( 1 rgmgm ?? ) of the amplifier will a ffect the time constant 1 and the loop operation will be unstable. if r1 is set to a higher value to improv e the gain of the amplifie r, the current through the transistor decreases and the gm results are smaller. this in turn affects the stabi lity of the loop filter. the capacitor c2 improves the dynamic range of the lpf. c2 is calculated taking into account the stability factor of the lpf circuit. c2 should be calculated from the time constant 22 1 rc c ? ? ? , with the condition n c ? ? )10~5( ? where n is the natural angular frequency given by the relation 1 ? ? ? v n ??? ? k is the phase detector constant and is given by the expression 6 1018.3 2 20 2 ? ???? x a i p ? ? ? ? k v is the vco sensitivity and is calculated as 6 min max min max 1015.83 6.00.4 75 120 2 2 x mhz mhz vv ff v ? ? ? ? ? ? ?? ? ? v/rad/s in this example, n = 1626 rad/s. so c = 16260 rad/s. choose c 2 = 0.047f. c 3 and r 3 form a low-pass filter to eliminate the sideband. the c of this filter is much higher than 10 n so the loop can be stable. free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 4.11. audio mute (pin 20) for the input control of the mute terminal, the v ih level is 0.8vcc to vcc and v il level is gnd to 0.2vcc. this can be controlled using a microcontroller (fig 8) or controlled with the ic?s vcc and an alternate switching control. (fig 9) figure 8: controlling mute with microcontroller figure 9: controlling mute with external switch 5. pilot signal adjust (pin 21) the phase of the pilot signal can be adju sted by changing the rc constant of r 1 and c 1 in-between pin 21 and ground. recommended settings are 1.8k ? for r 1 and 2.2nf for c 1 . 21 r 1 c 1 19 20 mute mpx vcc 5 18 17 6 19 shift register dual modulus divider micro-controller 20 mute mpx 5 free datasheet http://www.ndatasheet.com
analog product division PA1418 technical note 561 e elliot road. chandler, az 85225 tel: (480) 539-2900. fax: (480) 632-1715. www.protekanalog.com 5. pcb samples and recommendations: 24 tssop sample demo board: recommendations: ? it is important to note that the ground plane has been segragated into 3 semi-isolated sections to help isolate the rf output, the input and pl l lpf, and the digital sections. it is detrimental to signal integrity to allow these sections to share ground impe dence where it can be otherwise avoided. ? ideally, the bypass capacitors should be placed as close to the ic as possible and have the needed characteristics to handle the high frequencys of the circuit. ? when possible, using an independent power supply for t he digital system is useful to prevent noise from interfering with the other circuit blocks. ? the crystal oscillator should be placed as close as pos sible to the ic to minimize stray capacitance. it is also important to keep it clear of ot her signal traces or power lines that could interfere with it?s operation. ? the traces for the rf oscillator and the rf out put should be of suffecient width to reduce stray capacitance. (0.5mm wide minimum) ? it is important that the rf output should be isolated and not be allowed to cross any other signal paths, nor should it cross through vias or reflective trac e corners that can reduce signal strength and intergrity. free datasheet http://www.ndatasheet.com

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